In various electronic products, an integrated circuit chip (IC chip) is cooperatively used with other components. As known, the core voltage Vcore and the input/output voltage Vio of the IC chip are often different. Generally, a DC converter is employed to provide various DC voltages for the core circuit and the input/output circuit of the IC chip.
FIG. 1A is a schematic circuit diagram illustrating a conventional DC converter. As shown in FIG. 1A, the conventional DC converter 101 includes a driving stage 100 and an output stage 109. The driving stage 100 includes a driving circuit 104, a feedback pulse width modulation controller (also referred as a feedback PWM controller) 105, a voltage divider (R1, R2), a P-type power MOS transistor (P), and an N-type power MOS transistor (N). The output stage 109 includes an inductor L and a capacitor C.
The P-type power MOS transistor (P) and the N-type power MOS transistor (N) are electrically connected between the input/output voltage Vio and a ground terminal GND. The driving circuit 104 may issue two driving signals Sp and Sn to the gate terminals of the P-type power MOS transistor (P) and the N-type power MOS transistor (N), respectively. The inductor L is electrically connected between the drain terminals of the P-type power MOS transistor (P) and the N-type power MOS transistor (N), and the core voltage output terminal Vcore. The capacitor C and the voltage divider are both electrically connected between the core voltage output terminal Vcore and the ground terminal GND. The voltage divider is composed of two resistors R1 and R2. In addition, the voltage divider is used for providing a divided voltage Vd to the feedback PWM controller 105. Moreover, the feedback PWM controller 105 is used for providing a control signal Sc to the driving circuit 104. According to the control signal Sc, the pulse widths of the two driving signals Sp and Sn are modulated in order to stabilize the core voltage Vcore.
Take a system on chip (SOC) for example. The input/output voltage Vio received by the system on chip is 3.3V, and the core voltage Vcore received by the system on chip is 1.8V. Since the input/output voltage Vio and the core voltage Vcore are different, a DC converter is required to generate the core voltage Vcore.
FIG. 1B is a schematic circuit diagram illustrating an external power supply system for a conventional system on chip. As shown in FIG. 1B, the SOC 20 includes a core circuit 11 and an input/output circuit 13. A DC converter 15 is located outside the SOC 20. The configurations of the DC converter 15 are similar to those of the DC converter 101.
The actions of the DC converter 15 and the input/output circuit 13 of the SOC 20 are determined according to the input/output voltage Vio. According to the input/output voltage Vio, the DC converter 15 generates the core voltage Vcore to the core circuit 11. Therefore, the SOC 20 is operated according to the input/output voltage Vio and the core voltage Vcore.
As known, the SOC 20 is employed to integrate all circuits into a single chip. If the DC converter 15 is located outside the SOC 20, the fabricating cost will be increased.
In view of cost-effectiveness, it is important to integrate the DC converter into the SOC. FIG. 1C is a schematic circuit diagram illustrating the integration of a DC converter into a system on chip. As shown in FIG. 1C, the core circuit 113, the input/output circuit 116 and the driving stage 100 of the DC converter 112 are integrated into the SOC 10. However, since the output stage 119 of the DC converter 112 fails to be integrated into the SOC 10, the inductor L and the capacitor C need to be externally electrically connected to the SOC 10. The operating principles of the DC converter 112 are similar to those of the DC converter 101 of FIG. 1A, and are not redundantly described herein.
Moreover, for integrating the driving stage 100 into the SOC 10, the voltage-withstanding capability of the power MOS transistor should be taken into consideration. Since the core circuit 113 and the input/output circuit 116 are designed to be compatible with the CMOS semiconductor logic circuit fabrication process, the MOS transistors thereof are all low voltage-stress MOS transistors. For example, the low voltage-stress MOS transistor is designed to withstand a voltage of 1.8V.
However, as shown in FIG. 1C, the P-type power MOS transistor (P) and the N-type power MOS transistor (N) of the driving stage 110 should withstand a higher voltage (e.g. 3.3V). Consequently, for producing the SOC 10, the CMOS semiconductor logic circuit fabrication process and an additional deep n-well process are necessary to fabricate the high voltage-stress MOS transistor. Under this circumstance, the fabricating cost of the SOC 10 is still high.
Therefore, there is a need of providing an improved driving stage of the DC converter by using a fabrication process compatible with the CMOS semiconductor logic circuit fabrication process.